A paper by SPAN graduate student Joey Wilson, Andrew Nelson, and Behrouz Farhang has been accepted for publication in the IEEE Transactions on Circuits and Systems II. Joey performed most of the research for this paper while employed by L-3 Communications CSW in Salt Lake City, UT.
Modern implementations of discrete-time phase-locked loops (DT-PLLs) often contain delayed feedback. The delays are usually a side effect to pipelining, filtering, or other inner-loop mechanisms. Each delay increases the order of the system by introducing an additional pole to the closed-loop transfer function, and in many cases, makes the traditional type-2 loop equations obsolete. This paper describes how the second-order notions of damping and natural frequency can be applied to type-2 DT-PLLs in the presence of any number of delays. It provides equations for loop parameters that will provide a desired transient behavior based on damping and natural frequency, along with a test to ensure the accuracy of the results. The novelty of this work is that loop parameters can be found in closed-form and ensured to be accurate, without the need for human interaction, simulations, or numerical root-finding algorithms.
J Wilson, A. Nelson, B. Farhang, Parameter Derivation of Type-2 Discrete-Time Phase-Locked Loops Containing Feedback Delays, IEEE Transactions on Circuits and Systems II, Dec. 2009